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| AN628 APPLICATION NOTE DESIGNING A HIGH POWER FACTOR SWITCHING PREREGULATOR WITH THE L4981 CONTINUOUS MODE by Ugo Moriconi INTRODUCTION Conventional AC-DC converters usually employ a full wave rectifier bridge with a simple capacitor filter to draw power from the AC line. This "bulk" capacitor must be big enough to supply the total power during most of each half-cycle, while instantaneous line voltage is below the DC rectified voltage. Consequentely, the line current waveform is a narrow pulse, and the power factor is poor (0.5-0.6) due to the high harmonic distortion of the current waveform. If a high power factor switching preregulator is interposed between the input rectifier bridge and the bulk filter capacitor, the power factor will be improved (up to 0.99). Increasing in addition, the RMS current capability from the mains, reducing the bulk capacitor peak current and the harmonic disturbances. Switching at a frequency much higher than the line's one, the preregulator draws a sinusoidal input current, in phase with the input line voltage. There are several way that this can be accomplished. When the output voltage is higher than the input voltage (Vo > Vin), BOOST topology and continuos inductor current control mode are well suited to produce a good quality input sine current waveform. The input di/dt is low because the inductor is located between the bridge and the switch. This minimizes line noise and the line spikes will be absorbed by the inductor. Figure 1. L4981 Block Diagram February 2002 1/35 AN628 APPLICATION NOTE THE L4981 PFC CONTROLLER IC The L4981 integrated circuit is a continous mode average current controller with several specific functions for active power factor correction. It can operate in high quality, medium/high power conversion range and provides all the necessary features to achieve a very high power factor, up to 0.99. Thanks to the BCD technology used, operative switching frequency higher than 200kHz can be used. The L4981 can be used in systems with universal input mains voltage without any line switch. This new PFC offers the alternative of synchronization working at fixed frequency (L4981A), or working in modulated frequency (L4981B) to optimize the size of the input filter. Both devices control the conversion in average current mode PWM to maintain a sinusoidal line current without slope compensation. MAIN FEATURES: s s s s s s s s s s s Switching frequency higher than 200 kHz. Under Voltage Lockout with hysteresis and programmable turn-on threshold. Overvoltage and Overcurrent Protection. Precise (2%) on chip Reference externally available. Input/Output Synchronization (only for L4981A). Feed Forward Line and Load regulation. Universal input mains. Average current mode PWM. High Output Current totem pole driver. Low Start-up supply current. Soft Start. P.F.C. BOOST TOPOLOGY OPERATION The operation of the P.F.C. boost converter (see fig. 2) can be summarized in the following description. The A.C. line voltage is rectified by a diode bridge and the rectified voltage delivered to the boost converter. The boost converter section, using a PWM switching technique, boosts the rectified input voltage to a D.C. controlled output voltage (VO). The section consists of a boost inductor (L), a controlled power switch (Q), a boost diode (D), an output capacitor (CO) and, obviously, a control circuitry. Referring to the time-variable mains voltage (sine waveform), the converter produces a boost inductor average current like the rectified input voltage, changing continuosly the duty-cycle of the active switch (Q). The boosted D.C. voltage is controlled to a programmed value, higher than the maximum input instantaneous voltage (VIpk). Referring to the main currents shown in fig.2 schematic, the simplified formulae are (assuming: power efficiency = 1; output ripple voltage = 0; high frequency inductor ripple current = 0): 1) Peak inductor (L), switch (Q) and diode (D) currents PO I L pk = I Qpk = I Dpk = 2 ---------Vl pk 2) RMS inductor current I Lrms = PO 2 ---------V lpk 2/35 AN628 APPLICATION NOTE Figure 2. L D IQ Q ID IC CONTROLLER CO LOAD IO ~ IL ~ Cin D94IN119 3) RMS switch current PO 16 Vlpk I Q rms = ---------- 2 - ----------------------V lpk 3 VO 4) Average diode current IDavg = IO 5) RMS diode current PO 16 Vlpk ID rms = ---------- ---------------------V lpk 3 VO 6) Total RMS capacitor (CO) current 16 VO I C = I O ----------------------- - 1 3 VO 7) RMS twice line frequency capacitor current IO I C ( 2f )rms = -----2 8) RMS high frequency capacitor current 16 V O I C ( hf )rms = I O -------------------------- - 1.5 3 Vlp k The figure 3 shows the above mentioned quantities, normalized to the D.C. output current (IO), plotted versus VIpk / VO ratio. Moreover, the ILpk * ILrms normalized to IO2 value, related to the inductor energy (I2 * L), is plotted in the diagram (dotted line). This last plot gives an idea on the heavy increase of the inductor size operating with large input voltage range. Obviously, in real application the efficiency is less than 100% ( < 1). The output voltage ripple, related to the output capacitor (CO) is a parameter to be considered. The inductor high frequency current ripple (IL) is another parameter affected by the inductor value (L), the switching frequency (fsw) and the delivered power (PO). 3/35 AN628 APPLICATION NOTE Figure 3. ILp k I Lrms ---------------------------2 Io Figure 4. 4/35 AN628 APPLICATION NOTE CONTROLLER FUNCTION DESCRIPTION. The L4981 I.C. controls the conversion process with a continuous mode average current method, using two control loops (current loop and voltage loop) see fig. 5. Moreover, several internal functions ensure high quality conversion performance. A description of the internal blocks will be detailed in the design criteria section and pin description. However, referring to fig. 4, here below a brief description of the main functions is done: Multiplier block. This block produces an output current (programming current) as a product result of four different input signals (see fig. 13 for details). The multiplier output current, through a resistor connected to the negative side of a sense resistor, determines the error signal to the current loop. Figure 5. VOLTAGE CONTROL LOOP CURRENT CONTROL LOOP POWER STAGE LOAD LINE D94IN061 Figure 6. L REF 11 8.5V Iipk + OSC S Q R 1,10 Raux Iaux IPK Ripk I RS Ipk GND D94IN062A Operational amplifier blocks. Two amplifiers allow loop control. The first one (E/A), feeds back the output voltage (VO) and delivers its output to the multiplier block. The second (C/A), feeds back the line current and produces the reference for the PWM section. 5/35 AN628 APPLICATION NOTE PWM block. This block, comparing the sawtooth produced by the oscillator, with the reference signal from the C/A output, modulates its output signal duty-cycle. Its output, by the logic and driver sections, allows the controlled switch (Q) to modulate the inductor current. Logic block. Controls the flow from the PWM and the output with the Auxiliary function signals and soft start. Driver block. The driver supplies the gate current to turn on and off the power switch (Q). It delivers up to 1A peak current to allow high switching frequency applications. Aux functions. The Auxiliary functions allow to avoid overstress on power components of the application. Power supply block. This circuitry delivers the internal supply and references, recognizes the Undervoltage and Stand-by conditions to save consumption. P.F.C. BOOST DESIGN CRITERIA L4981 PIN DESCRIPTION AND BIASING CIRCUITRY. Pin 1. P-GND (Power stage ground). This pin, on the pc-board, has to be connected close the external Mosfet source. Pin 2. IPK (Overcurrent protection input). The current limitation is obtained with an internal comparator that holds down the output driver when the voltage at IPK input goes down to zero. In the L4981A, to preset the IPK input there is an internal current source (Iipk) of typically 85A. The maximum peak current (Ipk) can be programmed connecting (see fig. 6) a single resistor (Ripk) between this pin and the sense resistor (RS): R S I pk R ipk = -----------------I ipk In the L4981B, to preset the IPK input, an auxiliary resistor (Raux), connected from the VREF pin to the IPK pin, is required. The maximum peak current (Ipk) can be programmed choosing (see fig. 6) the resistances Raux and Ripk: R S I pk R ipk = -----------------I aux Where: VVREF -------------I aux = ---R a ux Note: If used with the L4981A, the auxiliary resistor avoids that the current source spread affects the precision of the protection simply getting an auxiliary current (Iaux) much higher than Iipk. 6/35 AN628 APPLICATION NOTE Pin 3. OVP (Overvoltage protection input). A comparator with a precise 5.1V reference voltage and 250mV of hysteresis, detects the overvoltage condition and turns the controller in stand-by condition (with low power consumption) and discharges the soft start capacitor. This pin (see fig. 7) has to be externally connected with a resistive divider (Ra and Rb) to the D.C. output voltage. The divider ratio is defined by the relation: V O + V OUT Ra ------- = --------------------------------- - 1 Rb 5.1V where: VOUT is the output overvoltage limit. Figure 7. Pin 4. IAC (A.C. current input). This pin (see fig. 8) has to be connected through a resistor to the rectified line voltage to drive the multiplier with a current (IIAC) proportional to the instantaneous line voltage: VI I IAC = --------Ra c The relation between the input alternate current (IIAC) and the output current (programming signal Imult) of the multiplier is described at MULT-OUT section (pin8). Figure 8. Pin 5.CA-OUT (Current amplifier output). The CA_OUT deliveres its signal to the PWM comparator. An external network (see fig. 9) defines the suitable loop gain to process the multiplier output and the line current signals. To avoid oscillation problem (see fig. 10) the maximum inductor current downslope (VO/L) has to be lower than oscillator ramp-slope (Vsrp * fsw): VO ------- R s Gc a V srp f sw L 7/35 AN628 APPLICATION NOTE where: Vsrp is the oscillator ramp peak-peak voltage. Gca is the current amplifier gain. fsw is the switching frequency. and rewritten as: Vs rp f sw L G ca -------------------------------VO R s Figure 9. OSC + C/A 8 9 5 PWM CA OUT Rf Ri' Ri Cf Rs D94IN063 Figure 10. defines the high frequency C/A gain (1 + ----- ): Rf Ri R f Vsrp f sw L ---- --------------------------------- 1 Ri V O RS To define the Cf value, it's useful to consider the current openloop gain, defined by the ratio between the voltage across Rs and the current amplifier output signal: v rs G avg = ------vca 8/35 AN628 APPLICATION NOTE Because, in worst condition is: Rs V O v rs = -----------------sL and the total variation of vca (the reference signal for PWM) is Vsrp: Rs V O G avg = ------------------------------------Vsrp 2 f L Multiplying this Gavg by Gca and solving for the crossover frequency (f = fc), follows: fs w fc = ------2 To ensure a phase margin (higher than 45), the zero frequency (fz) should be about --- , than: 2 fs w 1 2 f z = ---------- = ------------------------------- C f = -----------------2 Cf Rf 4 R f fs w fc Figure 11. Gain [dB] 100 80 60 40 Figure 12a. G ca G loop ~ RA RB VRMS RC 7 1/V2 CA CB D94IN064 20 0 -20 -40 -60 10 G av g 100 1000 f [Hz] 10000 100000 To avoid line current distorsion, the rectified mains ripple (2f) level has to be reduced. A two pole filter, with three resistors and two capacitors, setting the lowest pole at 2Hz and the highest one at 13Hz, is enough to get the useful voltage level reducing to 80dB the 100Hz gain. Pin 6. LFF (Load feed-forward input). This voltage input pin allows to modify the multiplier output current proportionally to the load in order to improve the response time versus load transient. The control is working with VLFF between 1.5V and 5.1V. If this function is not used, the LFF pin has to be connected to VREF pin.See also appendix A. Pin 7. VRMS. Input to the divider (1/V2RMS), it is especially useful in universal mains applications to compensate the gain variation related to the input voltage change. It will be connected to an external network (see fig. 12a) giving a voltage level proportional to the mains VRMS. The best control is reached using a VRMS voltage level in the range between 1.5V and 5.5V. Figure 12b. The signal (pin 7), with the network in fig. 12a is: 9/35 AN628 APPLICATION NOTE VRMS = 85V (110V -20%) VRMS = 260V (220V +20%) Gain at 2f(100Hz) VRM(7) = 1.6V VRM(7) = 5V -80dB Pin 8. MULT-OUT (Output of the multiplier). This pin deliveres the programming current (Imult) according to the relation: ( V va - o ut - 1.28V ) ( 0.8 V LF F - 1.28V ) I m ult = 0.37 I IAC --------------------------------------------------------------------------------------------------------2 VR MS where: VVA-OUT = E/A output voltage range VLFF = voltage input at pin 6 VRMS = voltage input at pin 7 IIAC = input current at pin 4 To optimize the multiplier biasing for each application, the relation between Imult and the other input signals to the multiplier are here reported (refer to figure 13 and see figures 13a to 13h). Figure 13. Figure 13a. MULTI-OUT vs. I C (VRMS = 1.7V; A VLFF = 5.1V) Figure 13b. MULTI-OUT vs. I C (VRMS = 2.2V; A VLFF = 5.1V) 10/35 AN628 APPLICATION NOTE Figure 13c. MULTI-OUT vs. I C (VRMS = 4.4V; A VLFF = 5.1V) Figure 13f. MULTI-OUT vs. I C (VRMS = 2.2V; A VLFF = 2.5V) Figure 13d. MULTI-OUT vs. I C (VRMS = 5.3V; A VLFF = 5.1V) Figure 13g. MULTI-OUT vs. I C (VRMS = 4.4V; A VLFF = 2.5V) Figure 13e. MULTI-OUT vs. I C (VRMS = 1.7V; A VLFF = 2.5V) Figure 13h. MULTI-OUT vs. I C (VRMS = 5.3V; A VLFF = 2.5V) 11/35 AN628 APPLICATION NOTE Pin 8 has to be connected through a resistor (Ri') to the negative side of Rs (see fig. 9) to sum the (IL * RS) and the (Imult * Ri') signals. The sum result is the error signal voltage to the current amplifier non inverting input. Ri' * Imult = Rs * IL Pin 9. ISENSE (Current Amplifier inverting input). This pin, is externally connected to the external network described at CA-OUT (pin 5). To be noted that Ri and Ri' have the same value because of the high impedance feedback network. Pin 10. SGND (Signal ground). It has to be connected, to the pc-board GND, close the filtering reference capacitor. Pin 11. VREF (Voltage reference). An internal bandgap circuitry, allows an accurate voltage reference. An external capacitor filter (from 100nF to some F) connected to the signal ground is recommanded (see fig. 14). This pin can deliver up to 10mA and can be used for external needs (e.g. enable for other circuits). Figure 14. Pin 12. SS (Soft start). This feature avoids current overload on the external Mosfet (Q) during the ramp-up of the output boosted voltage. An internal switch discharges the capacitor if output overvoltage or VCC undervoltage are detected. An internal current generator of 100 with the external capacitor define the soft start time costant (see fig. 15). Because the voltage at the softstart pin acts on the E/A output (driving the multiplier with VVAOUT = 5.1V typical voltage swing), the softstart time is defined by: V VA-OUT t SS = C ss ----------------------ISS Figure 15. 12/35 AN628 APPLICATION NOTE This time (tSS) depends on the application parameters (output voltage, input voltage, output capacitor value, boost inductor size, etc.) and normally the value amounts at some tens of msec. Pin 13. VVA-OUT (Error amplifier output). Output of the E/A that determinates the control of the boosted regulated voltage (VO). This pin has to be connected with a compensation network to the pin 14 (see fig.16). Figure 16. Figure 16a. First of all, the system does not have to attempt to regulate the twice mains frequency output voltage ripple (VO) to avoid the line current distorsion. Moreover the system stability has to be ensured. The voltage open loop gain can be splitt in two separated blocks. The first block small signal gain, is given by the ratio between the E/A output voltage (vea) and output voltage variation (vo) and is defined by the E/A network: vea 1 G ea' = --------- = -------------------------vo s R1 Cr Where Gea` is the E/A gain without R r ref. fig. 16. R2 has no effect on the error amplifier gain because the inverting input potential is fixed to VREF. The Gea can be seen also as the ratio between the error amplifier output ripple and the imposed output voltage ripple (VO). The E/A output signal can swing between 1.28V to 5.1V. A value less than 2.5% of the effective E/A output swing voltage (VVAOUT = 3.82V) could be chosen to fix the Cr. So, the Gea defined at the output voltage ripple frequency, determinates the Cr value to ensure the 100/120 Hz (2f) attenuation. 0.095V G ea -----------------V O V O 1 C r = ------------------------------------------------- - Ka ---------2 2f R 1 G ea R1 where: Ka = 1/60 for 50Hz and 1/72 for 60Hz mains frequency. Lower Cr value could increase harmonic distortion.The second block (Power block) is represented by the output filter capacitor (CO) with its own reactance (XCO), the system has to be able to compensate the total external load variation through the E/A output response (Vea). The power gain transfer function (Gpw), for large variations can be written: X CO G pw = IO -----------V ea The total load variation (IO) to be considered is: PO(max)/VO: 13/35 AN628 APPLICATION NOTE PO XC O PO 1 G pw = -------------------------- Gp w = -------------------------- --------------VO Ve a VO V ea s C O The voltage open loop gain contains two poles in the origin, then stability problem can arise. Connecting the resistor (Rr) in parallel to the capacitor Cr to shift the E/A pole from the origin to 1/(Rr * Cr), the stability is ensured. The crossover frequency fc can be calculated by Gpw * Gea` = 1 and therefore: fc = PO 1 --------------- -------------------------------------------------- -------------V O V ea 2 C O 2 R 1 Cr To allow the highest DC gain maintaining a phase margin of at least 22, the Rr maximum value is imposed as: 2.75 R r ------------------------2 fc C r The output filter capacitor value (CO) is related to the output voltage filtering (see Power section design). Pin 14. VFEED (Error amplifier input). This pin (see fig. 16), connected to the boosted output voltage through a divider, allows the output D.C. voltage regulation. Neglecting the contribution of the E/A feedback resistor (Rr), the 5.1V reference and the output DC voltage (VO) define the ratio between R1 and R2: VO R1 ------- = ------------ - 1 5.1V R2 To be considered that the R1, togheter with the feedback network(see pin 13 description) define the E/A gain. The R1/Rr ratio affects the load regulation (lower output current increases the output voltage) with the following relation: Vea R1 V Omax = -------------------------Rr where: VOmax is the maximum output voltage variation due to the E/A gain reduction and load variation. The R1 and R2 will be chosen in the high precision class: Pin 15. P-UVLO (Programmable supply undervoltage threshold). An internal divider (between pin 19, pin 15 and ground) and an internal comparator with a threshold voltage of 1.28V fixes the default turn-on and turn-off 15.5V and 10V levels of the supply section (see fig. 17). Using an external divider (RH and RL) it's possible to change the supply thresholds: RH fixes the hysteresis, RL fixes the turn-on threshold. To design a divider for a given supply threshold, is useful know (see fig. 17), the typical resistor value, useful to design the external divider, are: R1 = 394k, R2 = 88k and R3 = 58k. Anyway, in fig. 17a/b a diagram with threshold values and a table, useful for a fast choice of RH and RL are shown. For DISABLE function see Appendix B. 14/35 AN628 APPLICATION NOTE Figure 17. Programmable Under Voltage + UVLO 1.28V R1 19 RH P-UVLO RL - 15 R2 R3 10 D94IN066A VCCON and VCCOFF vs. RL VCC ON RH = RL * 6.8 VCC OFF 10V 10.1V 10.5V 10.8V 10.9V 11V RH 82k 220k 430k 909k 1.36M 2.7M RL 12k 33k 62k 133k 200k 390k 11V 12V 13V 14V 14.5V 15V a) b) Pin 16. SYNC (In/Out synchronization). Only for L4981A, this function allows the device to be synchronized with other circuits of a system (see fig.18a). When the device is externally synchronized, the external clock has to satisfy these conditions: the signal amplitude must cross the threshold value (3.5V), the frequency has to be slightly higher than that programmed by the R-C constant (see pin 18) and the pulse width has to be at least 800 nsec. If the device has to synchronize other circuits, the signal delivered by this pin is a positive pulse of 4.6V (0.5mA) and the pulse duration is equal to the sawtooth falltime. The L4981B uses this pin to perform another function. If the application does not use the SYNC function, it is preferrable to focus the EMI filtering problem using the B version. Pin 16, named FREQ-MOD in B version, allows to change the switching frequency in order to spread the energy content over a wider spectrum range. To perform the frequency modulation (see fig.18b), the pin must be connected, through a resistor (Rfm), to the rectified line voltage. This allows to change dinamically (cycle by cycle) the (COSC) charge and the discharge currents that define the ramp slopes of the oscillator sawtooth. The effect of the resistor produces the frequency change (see fig.18c) between the nominal value (fsw) and its minimum value which occurs when the input voltage reaches the peak value (VIpk). The total frequency variation (see also pin 17 and 18) can be estimated by the formula: fs w V IPK R osc ----------- = K -----------------------------f sw VRM S Rfm 15/35 AN628 APPLICATION NOTE where: Rfm is the programming current resistor. K is a constant value = 0.1157 for R value in K and fSW in KHz. sw A typical 20% ----------- can be a good compromise. f f sw Figure 18. a) 8.5V I Ifm 1.28V + 1/V MRS 200I 1 + 10I b) 17 ROSC ROSC VRMS 7 FREQ-MOD 2 POLES FILTER 16 COSC Rfm 18 COSC D94IN065A Modulation Frequency Normalzed in an Half Cycle of the Mains Voltage 1 Vl fsw 1 0.8 0.8 c) 0.4 0.4 0.2 0.2 0 0 45 90 0 135 180 Electrical degrees 16/35 AN628 APPLICATION NOTE Pin 17. ROSC (Oscillator resistor). An external resistor connected to ground, programs the charge and the discharge currents that pin 18 (COSC) forces to the external capacitor. The reference voltage at pin 17 is 1.28V (see fig.18a/b) To set the charge current, the relation is: 1.28V I c 10 --------------R OSC The discharge current is defined by: 1.28V I c 200 ---------------R OSC The maximum discharge current of Id = 12mA, this means a minimum Rosc value of 22K. Pin 18. COSC (Oscillator capacitor). An external capacitor (see fig 18a/b), connected between this pin and ground, fixes the rise and fall time (tr and tf) of the sawtooth oscillator according to the previous relations (pin 17) and therefore the switching frequency. The typical ramp valley-peak voltage (Vsrp) is fixed to 5V. The period T is defined by: 11 T = tr + tf = V srp CO SC ---- + --- I C Id the switching frequency is: 1 2.44 f sw = -- -----------------------------------T RO SC C OSC See also Fig. 19 Figure 19. Oscillator Diagram Pin 20. GDRV (Gate driver output). This output is internally clamped to 15V (see Fig. 20), to avoid ageing problems of the gate oxide. The output driver is normally connected to the gate of the power device through a resistor (say 5 to 50 Ohm) to avoid overshoot and to control the dI/dt of the switch. POWER SECTION DESIGN Booster Inductor The Boost Inductor design involves various parameters to be handled and there are different approaches to define them. In continuous mode operation, the energy stored in the boost inductor in each switching cycle, is not completely transferred to the output (bulk) capacitor. A quantity of energy is stored in the magnetic circuit, reducing in this way the input current ripple. This minimizes the line noise and reduces the input filter size (see fig.21). Pin 19. VCC (Supply voltage input). The very low current consumption feature before the turn-on threshold is reached. The undervoltage circuitry, with the threshold hysteresis of 5.5V typ. (see also pin 15) and an internal clamp at 25V (typ.) ensure the IC safety operation. 17/35 AN628 APPLICATION NOTE Figure 20. Figure 21. The energy transferred from the boost inductor to the bulk capacitor in each cycle is: 1 2 2 E/cycle = -- L ( I Lp - I Lv ) = L ILt I L 2 where: L = Boost Inductance ILp = Inductor Peak Current (ILt + IL/2) ILv = Inductor Valley Current (ILt - IL/2) ILt = Instantaneous Line Current (ILp + ILv)/2 IL = Twice Inductor Current Ripple (ILp - ILV) Because the instantaneous line current (ILt) that corresponds to the average inductor current in the cycle, draws a full rectified (half- sinusoidal) waveform, it is useful to refer to the AC line RMS and peak parameters: I Lpk = where: Irms = ILrms = PI/VIrms is the line current PI = PO/ is the input power is the power yeld. 2 I Lrms 18/35 AN628 APPLICATION NOTE The power transferred by the inductor in each cycle L I L t I L Pt = -------------------------ton where: ton = / fsw and = (VO - VIt) / VO For a given L, the twice ripple current IL is the quantity associated to the transferred energy and can be calculated as a certain percentage of the ILpk inductor current. V lt ( V O - V lt ) IL = -----------------------------------V O fs w L If the maximum Vlpk value is higher than the VO/2, the maximum IL occours when VIt = ------- and its value is 2 IL ( max ) VO = ----------------------4 f sw L VO If the Vlpk maximum value does not reach VO/2 voltage value, the maximum IL is reduced and its value is : V lpk ( VO - V lpk ) ------------- . IL ( max ) = --------------------------VO f sw L In continuous mode operation, an acceptable curent ripple level (Kr) can be considered between 10% to 35%. I L Kr = -----------------2 I Lpk Smaller current ripple on the inductor involves smaller noise on the rectified main bus reducing the input filter size; but the ripple reduction will impose an increase of the boost inductor. The high voltage, the flux density and the frequency range make the standard high frequency ferrite the most useful material in P.F.C. applications. To avoid the core saturation, related to the high permeability materials, it is necessary built an air-gap in order to allow an adequate magnetic force range (H+Hgap). An easy approach, is to have an approximated minimum value of core size that could be used to perform the conversion: L Volume K L I Lpk I Lpk + ------- 2 I where : K = specific energy constant. L = Boost inductor value in H. The specific energy constant (K), mainly depends on the ratio between the gap length (lgap) and the effective length (leff) of the magnetic core set and on the maximum B swing. Practically I e ff K 14 ---------Iga p can be used to get the minimum volume of the core set in cm3. After the minimum core-set size is estimated, the suitable type will be selected with technical and economic evaluations. Next step will be the design of the coil parameters. The above mentioned formula POt = -------------------------t on L I Lt I L 19/35 AN628 APPLICATION NOTE if referred to the magnetic path, can be rewritten : B P Ot = Ae Ie ff H -----ton where : Ae = effective area of the core section. leff = effective magnetic path length. B = deviated magnetic flux density. H = magnetic field strength. The ratio between the ferrite and the air path magnetic permeability, depends on the ferrite materials. Core materials for power application (such as B50/51), have a initial permeability value about 2500 times that of air. This means that, above a certain air-gap length percentage, it is possible to neglect the leff (length of the core) simplifing the calculation e.g. if a 1% of air-gap length, respect to the core lenght value is used, the error introduced is about 4%. B Rewriting P Ot = Ae I e ff H ------ t on B P Ot Ae Iga p H g ap -----ton --------equating to and simplifing P Ot = ----------------t on L I Lt I L Ae I g ap H gap B L IL t IL Because: Ig ap H gap N I L t and B = 0 H Ae N 0 H I IL I L H N ---------Igap and finally: L Igap ------------N --- 0 Ae This simplified relation is much easier to use than the complete one: Iga p I eff L -------------------------------------- + ----------------N ----- ------2 Ae o 0 Ae + -- I gap 4 After N has been defined, it's necessary to check the core for saturation of the magnetic path (rated N * I ax vs. m Air-gap on ferrites databook). If the check is too close the rated limit, an increase of the lgap (gap lengh) and a new calculation will be necessary. Copper losses RL * I2Lrms and former's winding space available will be considered for the wire selection. 20/35 AN628 APPLICATION NOTE An auxiliary winding can be used just to get a low cost supply for the I.C. It will be a low cost thin wire coil will be used and the number of turns is the only parameter to define. Input Bridge The input diodes bridge can be standard off-line, slow-recovery and low cost devices. The device selection considers just the input current (Irms) and the thermal data. Input Capacitor The input filter capacitor (CIN) has to sustain the input instantaneous voltage (VIt), with an imposed voltage ripple, during the turn-on (ton) time of the Mosfet. The worst conditions will be found at the minimum rated input voltage VIrms(min). The maximum high frequency voltage ripple (r = VI / VI) has to be imposed: I rms C IN Kr ------------------------------------------------ 2 f sw r Vlrms Where: Kr is the current ripple coefficient. r = 0.02 to 0.08. The CIN maximum value is limited to avoid current distortion. Output Bulk Capacitor The choice of the output bulk capacitor (CO), mainly depends on the electrical parameters that affect the filter performances and also on the subsequent application. The D.C. output voltage and overvoltage, the output power and voltage ripple are the first parameters to consider in all applications. The RMS capacitor ripple current IC(2f)rms = Io/ 2 and so, the output voltage ripple (VO) will be: 2 1 V O = I O ------------------------------------ + (ESR ) 2 ( 2 2f C O ) With a low ESR capacitor can be simplify: IO PO C O + --------------------------------- = -------------------------------------------- . 2 2f VO 2 2f VO V O Although the ESR, normally does not affect the output ripple parameter, it has to be considered in power losses account both for the rectified mains frequency and the switching frequency. If the application (i.e. computer supply) has to guarantee a specified Hold-Up time (tHOLD), the capacitance sizeing criteria will change: The CO has to deliver the supply energy for a certain time and a specific dropout voltage. 2 PO tH OLD C O = -------------------------------------------------2 2 V O_min - V op_min where: VO_min = minimum output voltage value (normally at the maximum load conditions) 21/35 AN628 APPLICATION NOTE Vop_min = minimum output operative voltage before the 'power fail' detection. Power Switch A power MOSFET is the active switch used in most application for its frequency features. It will be selected according with the output boosted voltage and the delivered power. There are two contributions for power losses in the mosfet: conduction losses and switching losses. The on-state power losses can be calculated using the formula: Pon-MOS = IQrms2 Rdson One extimation of the switching losses can be done considering two separated quantities: 1.5 1 2 10 P capaci tive ------ C o ss Vo + -- C ext V o fsw . 3 2 Pcrossover VO * Irms * tcr * fsw + Prec where: Coss is the Drain capacitance at VDS = 25V. tcr is the crossover time. Cext is the external layout stray capacitance. Prec is the contribution due to the diode recovery. To reduce the crossover losses a snubber network can be used. Booster diode The booster diode will be selected to withstand the output voltage and current. Moreover, it has to be as fast as possible in order to reduce the power switch losses.The STMicroelectronics TurboswitchTM diode series match this specifications, and are expecially suitable for this application. The diode power losses can be split in two contributions: conduction losses and switching losses. The conduction losses can be estimated by: PDon = Vto * IO + Rd * IDrms2 where: Vto = threshold voltage Rd = differential resistance Sense Resistor The sense resistor produces the signal for the current feedback loop and for the overcurrent protection circuit. An easy criterion to choose the sense resistanc e is to minimize the power dissipa ted assuring a sufficient signal to noise ratio. In much high power applications , it could be considered the magnetic sensing approach (see fig. 22). Figure 22. Magnetic Sense L iD iQ Co Rs -Vrs Load 22/35 AN628 APPLICATION NOTE DESIGN PROCEDURE. In order to fix the described concepts, here follows a brief description of a possible design flowchart referred to a typical "low-medium range power" PFC application. Design target specification: - Wide range mains; VINrms = 88 Vac to 264 Vac. - Pre-Regulated DC output voltage; V = 400 V. O - Rated output power; PO = 200W. The design starts fixing the operating conditions. - The switching frequency 100kHz /// - The 100Hz voltage ripple imposed at full load is 8V; this is satisfied selecting C = 100F out - The Over Voltage limit is set at Vout+50V - The maximum current ripple at nominal load has been chosen = 35% The circuit in fig. 23 can be proposed as reference for medium range power PFC application. Figure 23. Low-medium Power Typical Application(VO = 400V; PO = 200W) L 0.9mH R17 806K 1% R17 806K 1% C8 220nF 100V R6 620K 5% R7 360K 5% R6 620K 5% D3 R8 33K 5% C7 2N2222 220nF 100V DZ 22V 0.5W R23 R22 R19 1.1M 5% R19 1.1M 5% R15 10K R14 0.5W 56 Q2 0.5W STK2N50 D3 1N4150 C11 100F 25V D1 5TTA5060 R1 412K 1% R9 910K 1% + Vo C10 15nF 100V D4 1N4150 R1 412K 1% R9 910K 1% R20 10K 5% FUSE 4 BRIDGE 4 x BY214 Vi 88VAC to 254VAC NTC C1 220nF 400V 7 15 19 14 R12 220K 5% C9 330nF L4981A 2 13 3 D2 1N4150 R13 15 5% D5 BYT 11600 STH/STW15NB50 Q1 C12 270pF 630V R18 1.8K 4W R2 11K 1% C2 100F 450V R11 560 1% R21 5.1K 1% 8 5 R5 27K 5% R3 2.7K 5% RS C3 1nF R4 2.7K 5% C4 1nF R16 24K 1% C6 1F 16V C5 1F 16V 9 18 17 12 11 6 1 20 R10 21K 1% D93IN029C 0.07 2W 23/35 AN628 APPLICATION NOTE Input capacitor The input capacitor, placed across the rectified mains, must be considered as part of the EMI filter. The advantage, in placing this part after the mains rectification, is the shunt effect for the high frequency current in order to avoid it to flow throws the diodes of the bridge due to the poor recovery characteristic. On the other side, the value of this capacitor must to be held as low as possible because the inherent DC voltage content affects the harmonic distortion. With 220nF, the high frequency is filter enough and the introduced DC level can be considered not significant at reasonable load. Output capacitor For the output capacitor selection, it can be consider just the output voltage ripple. Choosing 100F/450Vthr 100/120Hz ripple is 8Vac Instead, if the pre regulated voltage bus must ensure enough energy for Hold-up requirements (i.e. the energy is delivered to a power supply system), the Coot value will be increased to around 180F. Sense resistor The sense resistance (Rest) is selected considering both, the signal level and the power dissipation parameters. Using 70m, the sense signal is good enough to be managed by the current loop. On the other side, the maximum power dissipation will be: Pros = RS * (Ilrms2 + Ilhfrms2) 0.5W Where Alarms max. = 2.50A Power Mos The Mosfet breakdown voltage is imposed; Bvdss Vout + Dvout + margin = 500V. The Rdson is selected taking in to account the conduction power dissipation. The formula for calculation is: Pon_max = Iqrms2 * Rdon i.e. considering Ron(t) = 0.7 the Pon_max = 2.15 * 0.7 = 3.3W. Adding the switching (and the capacitive) losses we can estimate 8W to 10W total power dissipation. Boost Diode The continuous current mode of operation, suggest using an Ultra-fast reverse recovery diode. The STMicroelectronics TURBOSWITCHTM family offers a good solution for this kind of application. Boost Inductor The inductor design starts defining the L value that is a function of the switching frequency and the accepted current ripple. In this design, we suggest an inductor value L = 0.75mH that can be realized using an ET3411 gapped set-core ferrite. 24/35 AN628 APPLICATION NOTE The results, concerning the described circuit, have been tested. And the result are shortly here reported: Vi (Vrms) 110 220 f (Hz) 60 50 Pi (W) 220 217 PF A-THD (%) H3 (%) 1.40 1.68 H5 (%) 0.40 0.83 H7 (%) 0.31 0.57 H9 (%) 0.28 0.48 VO (V) 392 398 VO (V) 8 8 PO (W) 201 204 (%) 91.6 94.2 0.999 0.997 1.79 2.25 DEMO-BOARD: Design process and Evaluation results In order to provide a powerful tool for the complete evaluation of the L4981, It is available a populated DemoBoard. The design process and the description for the demo, is here described. The demo has been designed to operate in wide range mains and the size and is finalized for a "medium-high" output power range. Let us start fixing the overall target of the application. Electrical target specification: - Wide range mains; VINrms = 88 to 264 Vac. - Regulated DC output voltage; V = 400 V. O - Rated output power; PO = 360W in any mains condition. - Target efficiency 90% in nominal load conditions. Chosen operation conditions of the application - The rectified mains (100/120Hz) full load voltage ripple is 7-8 V (peak to peak) this is achieved using an output capacitor Cout = 220Uf/450V - The maximum current ripple, in nominal load condition, is selected to be about 20%. This can be obtained using the boost inductor L = 0.55mH and setting the switching frequency at 100kHz. ## - The Over Voltage Protection has been set at V + 58V out The demo is capable to deliver around 400W output power; anyway in order to limit the temperature, the rated power is limited to 360W. The schematic is shown in fig 24. 25/35 AN628 APPLICATION NOTE Figure 24. Demo Board Circuit(VO = 400V; PO = 360W) B2= D1+D2 +D8+D9 R14 68 Dz1 18V VCC C10 150uF D4-STTH8R06 to220 (/40CW) NTC 2.5 V+ BU S=400V C2 330n R4 1.2M R6 500k R11 56k R12 56k L1=0.5mE42*21*15 gap=1.9 58/6 turns 20*.2mm VCC C11 220n D5STTA106 D6 DZW06-48 L2 3u C14 100n R18 6.8 2W R19 750k C3 330n F1 T15A250V R5 220k R7 500k R22 750k BRIDGE B1 8A R2 33k C8 100n R16 220k D7-STTA406 R20 750k R23 750k 88 to 264 Vac 7 Cf .22uF 600V C1 330nF 400V 4 1 19 13 14 3 D3 15 16 RAux1 L4981A/ B** 8 5 R10 5k C15 220uF 450V R17 15 Cs 330pF 20 6 ** RAux2 2 9 18 10 17 12 11 Q1+Q2# R21 19.6k Q4 4007 R25 1k 2W R24 16.9k TP1 R3 2.2k R8 17k C6 3.3n R13 2.2k C9 1n R15 24k C12 1u C13 1u R1 460 # // Q1&Q2 TO220*2 STM12NM50 / 7C/W R9 (RS) 50m // 3*0.15) Some design peculiarities A magnetic snubber solution has been adopted in order to limit/control the ramp rate of the current at the turnon edge of the Power Mos, referring to the schematic, the parts involved in this function are: L2, D5, D6, D7, C14 and R18. The function of the auxiliary inductor L2 is to reduce the ramp rate of the current reducing in this way the peak current, due to the recovery of the boost diode (D4), and the associate noise emission. The additional benefit of this magnetic snubber is also the reduction of the switching power dissipated in the Mos. D5 and D6 needs to provide a path that allows the demagnetization of the inductor L2, clipping the negative spike thus avoiding the Breakdown activation of the booster diode D4. D7, C14 and R18 will clamp the energy of L2 at the turn off edge of the Mos. The inrush current limiter NTC is placed between the cathode of the boost diode and the bulk capacitor C15. In this way, the current flowing in to the NTC limiter is the same of the boost diode well below the mains current especially at minimum mains value. The demo is provided with "self-supply" circuit. The proposed supply circuit, using a Graetz bridge is much efficient anyway; it can be inadequate when the output power is reduced down to less than 5W. On board, it has been recovered place for the Raux1 and Raux2. The two resistors will be connected in case of L4981B version evaluation. Here follows some comment concerning the design and the selection of the power parts of the demo. 26/35 AN628 APPLICATION NOTE Input capacitor selection The demo is not provided with complete dedicated EMI filter. At the input side, two parts compose the capacitor; the first (Cf.) is placed across the AC input of the bridge and the second one (C1) is tied to the rectified mains. The advantage, of this configuration is the minimization of the DC content in placing a low value after the mains rectification (C1), just to filter the high frequency. The capacitor Cf placed in the AC side must be considered as part of the EMI filter. Output capacitor selection For the output capacitor selection, it can be consider just the output voltage ripple. Choosing Co = 220F (450V), the maximum rectified mains ripple is: o V = ----------------------------------------- = 7.3V 200 Vo C o Sense resistor selection The sense resistance is set at 50mOhm (Rs = 3 * 0.15Ohm//) maximum power dissipation (@ 88Vac mains and 360W) will be: PRs(max) = RS * (Ilrms2 + Ilhfrms2) = 1.04W Where: Ilrms max. = 4.55A Power Mos In the selection of the power switch, it has been preferred to share the thermal dissipation in two separate TO220 packages. This is a good solution because the size of the heath sinkers can be limited. The breakdown voltage is imposed = 500V. Considering the On resistance (@ Tj = 100C) = 320 m the formula for the dissipated power calculation are: Conductive losses P_On(max) = IQ(max)2 * Rdon = 3.9 * 0.32 = 4.9W. Adding the capacitive (about 2.5W) and the switching losses (as low as 2-3 W, thanks to the snubber) we can estimate 10 to 12W total power dissipation at lower mains value. Boost Diode The 8A 600V chosen Turbuswitch fits well with the application. The power dissipa tedin the boost diode is about 1.4W. Boost Inductor The 0.55mH chosen inductor value allows a low ripple (23%) of its current; moreover, there is enough room (in the industrialization phase) to reduce the switching frequency holding an acceptable current ripple (e.g. reducing the frequency to 75 kHz the current ripple will be held within 30%. In this design, the coil has been realized with a gapped set-core ferrite E42*12*15. The results that can expect, realizing the described circuit, has been tested. And the result are shortly reported from Table 1 to Table 6. The PCB and component Layout can be seen in figgs 25, 26 and 27 (The Gerber files of the PCB are available on request). 27/35 AN628 APPLICATION NOTE Figure 25. Component Layout (Dimensions 88 x 150mm) Figure 26. P.C.B. Component Side (Dimensions 88 x 150mm) 28/35 AN628 APPLICATION NOTE Figure 27. P.C.B. Solder Side (Dimensions 88 x 150mm) DEMO BOARD TEST RESULTS Table 1. Maximum power range at 110Vac Vmains 88Vac 110Vac (*) 132Vac Pout 403W 407W 409W Vout 401Vdc 403Vdc 404Vdc Pin 433W 431W 430W THD 5.1% 2.2% 2.7% PF 0.998 0.999 0.999 Eff. .93 .945 .95 (*) Most significant losses balance at maximum power (110Vmains): - Power-mos (Q1+Q2) dissipated power = 9.6W. - Bridge (B1) dissipated power = 6.3W. - Boost turbo-diode (D4) dissipated power = 1.6W. - Boost inductor L1 = 2W - Aux. Inductor L2 = 1.6W. - NTC dissipated power = 1.1W. - Snubber = 1.4W 29/35 AN628 APPLICATION NOTE Table 2. Maximum power range at 220Vac Vmains 176Vac 220Vac (*) 264Vac Pout 415W 417W 419W Vout 407Vdc 408Vdc 409Vdc Pin 430W 431W 431W THD 4.2% 5.8% 7.4% PF 0.997 0.994 0.989 Eff. .965 .967 .972 (*) Most significant losses balance at maximum power (220Vmains): - - - - - - - Power-mos (Q1+Q2) dissipated power = 7.1W. Bridge (B1) dissipated power = 4W. Boost turbo-diode (D4) dissipated power = 1.3W. Boost inductor L1 = .6W Aux. Inductor L2 = 0.9W. NTC dissipated power = 0.8W. Snubber = 0.9W Table 3. Nominal power range at 110Vac Vmains 88Vac 110Vac (*) 132Vac Pout 366W 370W 372W Vout 404Vdc 406Vdc 407Vdc Pin 397W 395W 394W THD 5% 2.2% 3% PF 0.998 0.999 0.999 Eff. .92 .94 .945 (*) Most significant losses balance at nominal power (110Vmains): - - - - - - - Power-mos (Q1+Q2) dissipated power = 9.3W. Bridge (B1) dissipated power = 5.7W. Boost turbo-diode (D4) dissipated power = 1.5W. Boost inductor L1 = 1.8W Aux. Inductor L2 = 1.35W. NTC dissipated power = 1W. Snubber = 1.2W Table 4. Nominal power range at 220Vac V mains 176Vac 220Vac (*) 264Vac Pout 378W 381W 381W Vout 410Vdc 412Vdc 412Vdc Pin 394W 395W 395W THD 4.7% 6.4% 8.1% PF 0.997 0.993 0.987 Eff. .959 .964 .964 (*) Most significant losses balance at nominal power (220Vmains): - - - - - - - Power-mos (Q1+Q2) dissipated power = 6.9W. Bridge (B1) dissipated power = 3.5W. Boost turbo-diode (D4) dissipated power = 1.3W. Boost inductor L1 = 0.5W Aux. Inductor L2 = 0.83W. NTC dissipated power = 0.8W. Snubber = .8W 30/35 AN628 APPLICATION NOTE Table 5. Half power range at 110Vac V mains 88Vac 110Vac (*) 132Vac Pout 219W 220W 222W Vout 420Vdc 421Vdc 423Vdc Pin 239W 238W 237W THD 2.4% 3.6% 2.7% PF 0.999 0.999 0.999 .925 .937 Eff. (*) Most significant losses balance at half power (110Vmains): - - - - - - - Power-mos (Q1+Q2) dissipated power = 7.5W. Bridge (B1) dissipated power = 3.7W. Boost turbo-diode (D4) dissipated power = 1.1W. Boost inductor L1 = 1.3W Aux. Inductor L2 = 0.95W. NTC dissipated power = 0.7W. Snubber = 1W Table 6. Half power range at 220Vac V mains 176Vac 220Vac (*) 264Vac Pout 223W 223W 223W Vout 424Vdc 424Vdc 424Vdc Pin 236W 235W 235W THD 8% 10.5% 15% PF 0.993 0.994 0.978 Eff. .945 .949 .95 (*) Most significant losses balance at half power (220Vmains): - - - - - - - Power-mos (Q1+Q2) dissipated power = 5.64W. Bridge (B1) dissipated power = 1.9W. Boost turbo-diode (D4) dissipated power = 0.88W. Boost inductor L1 = .5W Aux. Inductor L2 = 0.6W. NTC dissipated power = 0.52W. Snubber = 0.7W Significant waveforms Since the described application is provided with a "magnetic snubber circuitry", it is of some interest to have a look at some switching waveform. In figure 28, it is depicted the power drain voltage and the current measured in L2 (aux. Inductor) . To be observed the "delay effect" of the current and the control of its slope. In fact, this circuitry allows to hardly reducing the Voltage-Current power crossing and the ramp rate of the drain current, reducing in this way the power dissipated inside the switch and the high frequency contents of the switching. In figure 29, it is shown both the switching edge and pointed the recovery charge due to the boost diode and the effect of the Voltage Clamp (D7, C14, R18). In figure 30, the switch-off edge is magnified and pointed out the effect of the RCD snubber to ground (Cs, Q4 R25) limiting the dV/dt and the above-mentioned Voltage Clamp. Finally, in figure 31, it is shown and pointed, in the reverse recovery region, the demagnetization effect of the D5+D6 and its control on the second slope of the recovery itself. 31/35 AN628 APPLICATION NOTE Figure 28. Figure 30. IL2-VDS waveforms at SWITCH-ON "Magnethic snubber effect" IL2-VDS waveforms at SWITCH-OFF and ON Recovery Peak current Drain voltage VDS = 100V/div. IL2 = 2A/div. Drain current slope control Current flowing in the Vol tage Clamp Figure 29. Figure 31. IL2-VDS waveforms at SWITCH-OFF Drain voltage snubber RCD effect Boost diode Anode voltage and IL2 Current Drain voltage Current flowing in the voltage Clamp 0V Negative Voltage for L2 demagnetization Miscellaneous: The 360W Demo Board is replacing a previous 200W version. It is possible to order this tool quoting the order code EVAL4981A. The board comes with a CDROM containing the inherent documentation and a special program dedicated to the ST PFC controllers (L4981 and L6561) that make it easy the design of these applications. 32/35 AN628 APPLICATION NOTE APPENDIX A LFF (pin 6) Function. Since in Power Factor applications the Error Amp. compensation network has to filter the mains frequency contents, in order to reduce harmonic distortions, the crossover frequency of the loop gain must be low. This involves a poor load transient response. An additional function (LFF) is available in L4981A/B devices. It is expecially suitable to modify the multiplier output current, proportionally to the load, in order to improve the system response bypassing the E/A.The control is working with VLFF voltage between 2V and 5.1V. In fig. 32 is shown an application example to explain this function. An external OP-AMP has been used to get the suitable signal voltage avoiding sense resistor (R1) power dissipation. In the real application the sense resistor is often replaced by sense transformer. Figure 32. Application example L IL IQ Q pin6 (VLFF) VREF=5.1V 3.6K R3 LM258 + VO D95IN206B ~ D ID IC IO LOAD CO R1 10K L4981 ~ VCC 10K R2 Design criteria: It is avisable to ensure a minimum VLFF 2V at the minimum output current.Since the OP-AMP (LM258) Vol = 0.7V (@ 1mA), to get the minimum voltage at VLFF, 1.3V has to be added. A resistor devider tied to the reference voltage (pin 11 of the controller) shifts the output of the OP-AMP. ---------------- R 3 R 3 = 1.3k therefore 1.3V = -------------------The OP-AMP supply voltage is the same used for PFC controller (VCC) and its gain if fixed in order to produce VO = 5.1V at the maximum load (IO max). ( 5.1V - 0.7V ) R 3 + 3.6k R2 VO = R 1 IOmax 1 + --------- = 5.1V 10k E.g. for IOmax = 3A. R1 = 0.1 - 1W R2 is roughly 160K. 33/35 AN628 APPLICATION NOTE APPENDIX B Disable Sometimes it is useful to disable the controller. For example, in a complete system in which a PWM regulator follows the PFC stage, at low output power it is advantageous to shutdown the PFC section to improve the overall system efficiency (stand-by / sleep mode). Likewise most of controllers, one way to do this (using L4981A/ B), is pulling down either the Soft-Start or the E/A output pin . In addition the L4981A/B can be disabled grounding the P-UVLO (pin 15) see fig 33.The P-UVLO function has been designed to program the supply thresholds by means of an external divider (see application note for details) but it can be effectively used for this purpose forcing a voltage below the internal reference (1.28V).Besides turning off the driver output stage this method puts the controller in "before start-up" condition and gives the advantage of minimizing the supply consumption of the IC. Figure 33. + UVLO 1.28V R1 19 RH P-UVLO RL DISABLE - 15 R2 R3 I 1mA 10 D95IN281B 34/35 AN628 APPLICATION NOTE Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http:/ /www.st.com 35/35 |
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